1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to substrate diodes of complex SOI circuits, which may be used for thermal sensing applications and the like.
2. Description of the Related Art
The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the latter aspect renders the reduction of the channel length, and associated therewith the reduction of the channel resistivity, a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
In view of the former aspect, in addition to other advantages, the semiconductor or silicon on insulator (SOI) architecture has continuously been gaining in importance for manufacturing MOS transistors, due to their characteristics of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region, in which the drain and source regions as well as the channel region are located, also referred to as the body, is dielectrically encapsulated. This configuration provides significant advantages, but also gives rise to a plurality of issues. Contrary to the body of bulk devices, which is electrically connected to the substrate and thus applying a specified potential to the substrate maintains the bodies of bulk transistors at a specified potential, the body of SOI transistors is not connected to a specified reference potential, and, hence, the body's potential may usually float due to accumulating minority charge carriers, unless appropriate countermeasures are taken.
A further issue in high performance devices, such as microprocessors and the like, is an efficient device-internal temperature management due to the significant heat generation. Due to the reduced heat dissipation capability of SOI devices caused by the buried insulating layer, the corresponding sensing of the momentary temperature in SOI devices is of particular importance.
Typically, for thermal sensing applications, an appropriate diode structure may be used wherein the corresponding characteristic of the diode may permit information to be obtained on the thermal conditions in the vicinity of the diode structure. The sensitivity and the accuracy of the respective measurement data obtained on the basis of the diode structure may depend significantly on the diode characteristic, i.e., on the diode's current/voltage characteristic, which may depend on temperature and other parameters. For thermal sensing applications, it may, therefore, typically be desirable to provide a substantially “ideal” diode characteristic in order to provide the potential for precisely estimating the temperature conditions within the semiconductor device. In SOI devices, a corresponding diode structure, i.e., the respective PN junction, is typically formed in the substrate material located below the buried insulating layer, above which is formed the “active” semiconductor layer used for forming therein the transistor elements. Thus, at least some additional process steps may be required, for instance for etching through the semiconductor layer or a corresponding trench isolation area and through the buried insulating layer in order to expose the crystalline substrate material. On the other hand, the process flow for forming the substrate diode is typically designed so as to exhibit a high degree of compatibility with the process sequence for forming the actual circuit elements, such as the transistor structures, without undue negative effects on the actual circuit elements.
In sophisticated semiconductor devices, there is an ongoing demand for reducing feature sizes of the circuit elements in order to enhance transistor performance and increase packing density of the device. Thus, respective process sequences including sophisticated lithography, etch, deposition, implantation, anneal and other process techniques may have to be frequently adapted or newly developed in order to obtain the desired gain in transistor performance. For example, in sophisticated applications, the drive current capability of MOS transistors may not only be increased by continuously reducing the gate length of the respective transistor devices but also by increasing the charge carrier mobility in the respective channel regions of the transistors. This may be accomplished by locally generating a corresponding strain in the channel region which may, if appropriately adapted to the crystallographic conditions in the channel region, result in an increase of electron mobility and hole mobility, respectively, thereby providing the potential for significantly enhancing the performance of P-channel transistors and N-channel transistors. Thus, a plurality of respective mechanisms have been developed in order to create the desired type of strain in respective transistor elements. For instance, semiconductor materials may be provided in the drain and source regions and/or within the channel region in order to obtain a specific slight lattice mismatch, which may result in an appropriate strain in the channel region. In other approaches, in addition or alternatively to the former mechanisms, highly stressed materials may be positioned in the vicinity of the channel region to induce a corresponding strain therein. For this purpose, frequently the contact etch stop layer, which is formed above the transistor element after completing the basic transistor structure, may be efficiently used since this layer is located close to the channel region and may be provided in the form of a dielectric material, such as silicon nitride, which may be efficiently deposited with a high intrinsic stress. Furthermore, respective deposition and patterning regimes have been developed by which locally different types of strain may be induced in different transistor elements.
In addition to or alternatively to strain-inducing mechanisms, many other process adaptations, for instance with respect to patterning strategies, implantation processes, anneal sequences and the like, may allow a significant improvement of the transistor performance but may have a detrimental effect on the substrate diode, which may prevent respective improvements with respect to transistor performance to be implemented in the overall process flow due to a significant deviation of the diode characteristic which would then significantly affect the sensing capability of the diode structure.
With reference to FIGS. 1a-1c, a typical process will now be described, in which a process sequence designed to enhance the transistor performance in the active semiconductor layer of an SOI device may have significant adverse effects on the diode structure formed in the substrate material, thereby significantly reducing production yield and thus profitability. In the example illustrated, the transistor performance may be improved by reducing the series resistance within the transistor and enhancing the stress transfer mechanism provided by a stressed dielectric layer formed above the transistor.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 representing an SOI device. The device 100 comprises a substrate 101 which includes, at least in an upper portion thereof, a substantially crystalline substrate material 102, which may be pre-doped in accordance with device requirements. For instance, the substrate material 102 may have incorporated therein a moderately low concentration of a P-type dopant. Furthermore, in an area of the substrate material 102 corresponding to a first device region 110, a respective counter-doped well 103 may be provided in which a corresponding substrate diode is to be formed. Furthermore, the semiconductor device 100 comprises a buried insulating layer 104, for instance comprised of silicon dioxide and the like, which separates a semiconductor layer 121 from the substrate material 102. The semiconductor layer 121 may represent a substantially crystalline semiconductor material, for instance silicon, silicon/germanium or any other appropriate silicon-based material for forming therein and thereon a plurality of circuit elements, such as transistors 130, which are illustrated at an early manufacturing stage. As shown, the transistors 130 may include respective gate electrodes 131 having formed on sidewalls thereof, in this manufacturing stage, a spacer 132, which may be designed to provide a desired offset during an implantation process for forming extension regions 134. Furthermore, the transistors 130 comprise a gate insulation layer 133 separating the gate electrode 131 from a channel region 135 formed in the semiconductor layer 121. Furthermore, in this manufacturing stage, an increased dopant concentration of a dopant species also provided within the channel region 135 may be positioned in the vicinity of the extension regions 134, wherein such increased dopant concentrations may also be referred to as halo regions 136, provided to obtain desired abrupt PN junctions after completing the transistor elements 130. Furthermore, respective isolation structures 105 in the form of trench isolations are provided in order to define specific areas in the first and second device regions 110, 120 wherein, for convenience, respective isolation structures 105, laterally bordering respective transistors 130, are not shown in the second device region 120. In the first device region 110, the isolation structures 105, in combination with a respective portion of the buried insulating layer 104, define respective openings 111A, 111B extending to the substrate material 102, i.e., an exposed portion of the well 103.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. After providing the substrate 101 and defining therein respective doped areas in the substrate material 102, such as the N-well 103, which may be accomplished on the basis of appropriate implantation sequences, the isolation structures 105 may be formed by using well-established photolithography, anisotropic etch, deposition and planarization techniques. It should be appreciated that, depending on the process strategy, the isolation structures 105 in the first device region 110 may be formed as a substantially continuous insulating portion or may expose respective semiconductor portions of the initial semiconductor layer 121. Next, the gate insulation layers 133 and the gate electrodes 131 may be formed on the basis of sophisticated oxidation and/or deposition techniques followed by the deposition of a gate electrode material, which may then be patterned on the basis of sophisticated lithography and respective etch processes. It should be appreciated that respective gate electrode materials may also be provided in the first device region 110 and may be patterned in accordance with device requirements. For convenience, any such patterned gate electrode materials, which may be used for providing intra-level interconnections are not shown in FIG. 1a. Next, the spacer 132 may be formed on the basis of oxidation and/or deposition techniques and subsequently respective implantation processes, such as pre-amorphization implants, a halo implantation and the like, may be performed, thereby providing the halo regions 136. It should be appreciated that respective implantation processes have to be performed differently for transistors of different conductivity types. That is, respective resist masks may be provided prior to a specific ion implantation process in order to prevent unwanted dopant species from being introduced into specific transistor elements. For example, during the halo implantation, a P-type dopant may be introduced into the active region of an N-channel transistor, while respective P-channel transistors are covered by a resist mask. Next, a further implantation sequence may be performed in order to provide the extension regions 134, wherein the spacers 132 provide the desired offset to the channel region 135. Thereafter, the openings 111A, 111B may be formed on the basis of appropriate anisotropic etch techniques using a resist mask for etching through the material of the semiconductor layer 121 or through the material of the isolation structure 105, when provided as a substantially continuous area within the first device region 110. Furthermore, the corresponding etch process is designed to etch through the buried insulating layer 104 and exposing material of the N-well 103.
FIG. 1b schematically illustrates a cross-sectional view of the semiconductor device 100 in a further advanced manufacturing stage. The transistors 130 may have formed a sidewall spacer structure 136 and respective deep drain and source regions 137. Similarly, a respective sidewall structure 116 may be formed within the openings 111A, 111B and corresponding heavily doped regions 117A, 117B may be formed in the N-well 103.
In order to provide a high degree of compatibility of the process of forming the substrate diode structure in the first device region 110, with respect to the further processing of the transistors 130, the respective manufacturing processes are performed in the first and second device regions 110, 120 in a common process sequence. Thus, the sidewall spacer structure 136 may be formed on the basis of well-established spacer techniques, i.e., by depositing an appropriate material layer or layer stack and patterning the corresponding layer by anisotropic etch techniques. Thus, the layer is also deposited within the openings 111A, 111B, thereby resulting in the sidewall spacer structure 116 after the anisotropic etch process. Next, the deep drain and source regions 137 may be formed by a corresponding ion implantation sequence, for instance by first covering P-type transistors in the second device region 120 and also covering the opening 111B and introducing an N-type dopant, thereby obtaining the deep drain and source regions 137 of the N-channel transistors and also obtaining the heavily doped region 117A. Thereafter, a corresponding implantation process may be performed on the basis of a P-dopant species. Next, respective anneal sequences may be performed to activate the dopants and also to re-crystallize implantation-induced damage in the drain and source regions 137 and the heavily doped regions 117A, 1117B.
As previously explained, several mechanisms may be implemented in order to improve transistor performance in the second device region 120. For instance, the series resistance in the respective transistors 130 may be reduced by placing a corresponding metal silicide to be formed in the drain and source regions 137 more closely to the channel region. Thus, the spacer structure 136 may be removed prior to a respective silicidation process, wherein additionally a stressed dielectric material may also be formed more closely to the channel region after the silicidation process.
FIG. 1c schematically illustrates the semiconductor device 100 with respective metal silicide regions 138 formed in the respective transistors 130 with a reduced lateral offset with respect to the channel regions 135. Similarly, respective metal silicide regions 118 may also be formed in the doped regions 117A, 117B. Prior to the respective silicidation process, the spacer structure 136 may be removed on the basis of well-established etch techniques, wherein the spacer structures 116 are also removed. However, after the removal of the spacer structures 116, the formation of the respective metal silicides 118 may be highly critical, since the characteristics of a substrate diode 140, defined by the PN junction of the region 117B and the N-well 103, are substantially determined by the dopant concentration in the vicinity of the PN junction. During the preceding manufacturing sequence, a certain overlap of the regions 117A, 117B with the corresponding material of the buried insulating layer 104 may have been created, in particular in the P-doped region 117B due to dopant diffusion during the corresponding anneal processes. However, since the metal silicide regions 118 are formed without the spacer structure 116 (see FIG. 1b), the remaining overlap 119 of the P-type dopant of the area 117B with buried insulating layer 104 may provide only a small process margin for the silicidation process, which may even result in a shortage of the respective PN junction due to the migration of metal silicide into the lightly N-doped well 103. Even if a corresponding shortage may not occur, the resulting characteristics of the PN junction may nevertheless significantly depend on the process specifics of the silicidation process, since the distance of the respective metal silicide region 118 with respect to the PN junction in the areas 119 may vary and therefore also affect the corresponding diode characteristics. Furthermore, during the silicidation process, which may require the deposition of a refractory metal, cleaning processes may typically be performed, which may damage the corresponding sidewalls of the openings 111A, 111B thereby possibly further reducing an overlap between the P-doped region 117B and the corresponding insulating material of the layer 104 in the area 119. Consequently, the substrate diode 140 may have to be formed on the basis of significantly reduced process margins, when a corresponding process sequence for enhancing the performance of the transistors 130 is performed. It should be appreciated that a corresponding “shortage” in the region 117A is less critical since the behavior of the substrate diode 140 is substantially defined by the PN junction defined by the N-well 103 and the region 117B.
Thus, the performance gain obtained by the reduced series resistance in the transistors 130 and by the close proximity of a stressed dielectric layer 139, for instance in the form of a silicon nitride layer, may be obtained at the cost of reduced reliability of the substrate diode 140. As a result, the conventional process technique for forming the substrate diode 140 may suffer from reduced process margins with respect to process variations in forming high performance transistor elements.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.